Sense amplifier

ABSTRACT

A sense amplifier comprising two asymmetrical differential amplifiers connected to each other in such a way that their outputs are accelerated to charge up one another by utilizing nodes at which potentials are changed in response to a change of the input signal supplied from a pair of bit lines or a pair of data lines, whereby the operating speed of the sense amplifier is increased.

BACKGROUND OF THE INVENTION

The present invention relates to a sense amplifier, and moreparticularly to a complementary metal-oxide semiconductor (CMOS)high-speed sense amplifier for amplifying a potential difference betweena pair of bit lines or a pair of data buses in a static semiconductormemory.

Accompanied by the recent developments in the high integration ofsemiconductor memories, each transistor constituting a memory cell hasbecome more and more miniaturized. This miniaturization has reduced thedriving capability of a transistor, lowered the speed of the potentialchange, during reading, of a pair of bit lines or a pair of data busesconnected to a sense amplifier, and decreased the potential differencebetween a pair of bit lines or a pair of data buses. To detect thethusly decreased and slowly changing potential difference between a pairof bit lines or a pair of data buses, an improved high-speed senseamplifier is necessary.

A conventional sense amplifier cannot provide a high-speed operationwith such a decreased and slowly changing potential difference, becauseof a long rising period and a large amplitude of the output signal, asdescribed later in more detail.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide a senseamplifier which can operate at a high speed in response to a change of apotential of a pair of bit lines or a pair of data lines.

Another object of the present invention is to provide a sense amplifierwhich can change the output potential at a high speed in response to achange of a potential of a pair of bit lines or a pair of data lines.

To attain the above objects, the present invention employs twoasymmetrical differential amplifiers connected to each other in such away that their outputs are accelerated, to charge up one another byutilizing nodes at which potentials are changed in response to a changeof the input signal supplied from a pair of bit lines or a pair of datalines.

According to the present invention, there is provided a sense amplifiercomprising a pair of differential amplifier circuits each including apair of differential input transistors for receiving complementarysignals and a feedback transistor connected to a commonly connectingpoint of the pair of differential input transistors and having a controlinput connected to an output of one of the differential inputtransistors. The complementary signals applied to one of the pair ofdifferential amplifier circuits have phases opposite to the phases ofthe complementary signals applied to the other of the pair ofdifferential amplifier circuits. At least one of the pair ofdifferential amplifier circuits has a first output pull up transistorand a second output pull up transistor connected in parallel between apower supply and an output end. The first output pull up transistor hasa control input connected to the control input of the feedbacktransistor. The second output pull up transistor has a control inputconnected to an output of the feedback transistor in the other of thedifferential amplifier circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects, features, and other advantages of the presentinvention will become more apparent from the following description ofthe embodiments with reference to the accompanying drawings, wherein:

FIG. 1 is a circuit diagram showing a conventional sense amplifier;

FIG. 2 is a circuit diagram showing a part of a semiconductor memorydevice to which the present invention is applied;

FIG. 3 is a waveform diagram showing the operation of the device shownin FIG. 2;

FIG. 4 is a circuit diagram showing a sense amplifier according to anembodiment of the present invention;

FIG. 5 is a waveform diagram showing an example of the operation of thecircuit shown in FIG. 4; and

FIG. 6 is a waveform diagram showing another example of the operation ofthe circuit shown in FIG. 4.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Before describing the embodiment of the present invention, aconventional sense amplifier will first be described with reference toFIG. 1. In FIG. 1, the conventional sense amplifier consists of twoasymmetrical differential amplifiers D₀₁ and D₀₂. The first differentialamplifier D₀₁ includes N-channel input transistors Q₀₁ and Q₀₂,P-channel pull-up transistors Q₀₃ and Q₀₄, and an N-channel feedbacktransistor Q₀₅. A pair of bit lines BL and BL are connected to the gatesof the input transistors Q₀₁ and Q₀₂, respectively. An output signal DAis obtained at a commonly connecting point between the drain of theP-channel pull-up transistor Q₀₃ and the drain of the N-channel inputtransistor Q₀₂. The second differential amplifier D₀₂ has the sameconstitution as the first sense amplifier unit D₀₁ and includestransistors Q₀₁ ' through Q₀₅ '.

When the bit line BL is at a high potential (H) and the bit line BL isat a low potential (L), in the first differential amplifier D₀₁, thetransistor Q₀₁ has a high mutual conductance g_(m) (H) and thetransistor Q₀₂ has a low mutual conductance g_(m) (L). Therefore, theP-channel pull up transistors Q₀₃ and Q₀₄ receive a low potential attheir gates and have the high mutual conductance g_(m) (H). Thus, theoutput signal DA is at a high level. The feedback transistor Q₀₅receives a low potential at its gate and has the low mutual conductanceg_(m) (L), ensuring the high level of the output signal DA. In contrast,in the second differential amplifier D₀₂, the transistors Q₀₁ ', Q₀₃ ',and Q₀₄ ' have the low mutual conductance g_(m) (L), and the transistorsQ₀₂ ' and Q₀₅ ' have the high mutual conductance g_(m) (H), so that theoutput signal DA is at a low level.

Contrary to the above, when the bit line BL is at an L level and the bitline BL is at an H level, it will be easily seen that the output signalDA is at an L level and the output signal DA is at an H level.

The conventional sense amplifier shown in FIG. 1, however, has adisadvantage of low-speed operation. That is, it takes a considerablylong period from a time at which a pair of bit lines inverts itspotential to a time at which a pair of the output potentials of thesense amplifier are inverted. This is because the output potential israised only by the single pull-up transistor Q₀₃ or Q₀₃ ', and theoutput potential is lowered only by the single transistor Q₀₂ or Q₀₂ '.Another reason for the low-speed operation is that the amplitude of theoutput signal DA or DA, which is determined by the transistors Q₀₃, Q₀₂,and Q₀₅, is relatively large.

FIG. 2 shows a part of a semiconductor memory device to which thepresent invention may be applied. FIG. 3 is a waveform diagram showingthe operation of the device shown in FIG. 2. Referring to FIGS. 2 and 3,when clock signals φ₁ and φ₂ are applied to the gates of prechargingtransistors Q₃ and Q₁₀, bit lines BL and BL, and data lines DL and DLare shortcircuited. In this example, the bit lines BL and BL areprecharged through transistors Q₁ and Q₂ to have a high potential. Then,when a word line, for example, a word line WD₁ is selected to be a highpotential, one of the bit lines BL and BL, for example, BL, is turned tohave a low potential, depending on the contents of a selected memorycell. The potential of the other bit line BL is not changed in thisexample. After this, when a bit-line selecting signal BS is applied tothe gates of transfer-gate transistors Q₈ and Q₉, the potentials of thebit lines BL and BL are transferred through the transistors Q₈ and Q₉ tothe data lines DL and DL. A sense amplifier SA amplifies the potentialdifference between the data lines DL and DL. According to the presentinvention, the sense amplifier SA is improved, as is later described indetail.

Another example of a semiconductor memory device is known in which apair of bit lines are precharged to have an intermediate potentialbetween a high potential and a low potential.

As will be described later in more detail, the present invention iseffective whether a pair of bit lines are precharged to have a highpotential or to have an intermediate potential.

An embodiment of the present invention will now be described in detailin the following.

FIG. 4 is a circuit diagram showing a sense amplifier according to anembodiment of the present invention. In FIG. 4, a sense amplifier SAconsists of a first differential amplifier D₁ and a second differentialamplifier D₂. The first differential amplifier D₁ comprises a firstinput transistor Q₁₁, a second input transistor Q₁₂, a first output pullup transistor Q₁₃, a pull up transistor Q₁₄, a feedback transistor Q₁₅,and a second output pull up transistor Q₁₆. In this embodiment, thetransistors Q₁₃, Q₁₄, and Q₁₆ are P channel metal-oxide semiconductor(MOS) transistors, and the transistors Q₁₁, Q₁₂, and Q₁₅ are N channelMOS transistors. A bit line BL is connected to the gate of the firstinput transistor Q₁₁. A bit line BL is connected to the gate of thesecond input transistor Q₁₂. The drain of the first input transistor Q₁₁is connected to the gate and the drain of the pull up transistor Q₁₄, tothe gate of the first output pull up transistor Q₁₃, and to the gate ofthe feedback transistor Q₁₅. The source of the pull up transistor Q₁₄ isconnected to a power supply V_(CC). The drains of the first and thesecond output pull up transistors Q₁₃ and Q₁₆ are connected to the drainof the second input transistor Q₁₂. The sources of the first and thesecond input transistors Q₁₁ and Q₁₂ are connected to the drain of thefeedback transistor Q₁₅. The source of the feedback transistor Q₁₅ isconnected to a ground line V_(SS). An output end DA is connected to apoint between the drains of the output pull up transistor Q₁₃ or Q₁₆ andthe second input transistor Q₁₂.

The second output pull up transistor Q₁₆ is provided according to thepresent invention.

The circuit constitution of the second differential amplifier D₂ issimilar to that of the first differential amplifier D₁, and includes afirst input transistor Q₂₁, a second input transistor Q₂₂, a firstoutput pull up transistor Q₂₃, a pull up transistor Q₂₄, a feedbacktransistor Q₂₅, and a second output pull up transistor Q₂₆. It should benoted, however, that, in contrast to the first differential amplifierD₁, the second differential amplifier D₂ receives a signal on the bitline BL at the gate of the second input transistor Q₂₂ and receives asignal on the bit line BL at the gate of the first input transistor Q₂₁.The signals on the bit lines BL and BL, after the bit lines areselected, are complementary. The abovementioned difference lies in thefact that the complementary signals applied to the first differentialamplifier D₁ have phases opposite to the phases of the complementarysignals applied to the second differential amplifier D₂.

According to the present invention, an output amplitude determiningtransistor Q₂₀ is provided between the sources of the output pull uptransistors Q₁₃, Q₁₆, Q₂₃, and Q₂₆ and the power supply V_(CC). Thetransistor Q₂₀ in this embodiment is a P-channel MOS transistor. Thesource of the transistor Q₂₀ is connected to the power supply V_(CC).The drain of the transistor Q₂₀ is connected to the sources of thetransistors Q₁₃, Q₁₆, Q₂₃, and Q₂₆. The gate of the transistor Q₂₀ isgrounded. Accordingly, the transistor Q₂₀ is normally in a conductivestate.

The sources of the input transistors Q₁₁ and Q₁₂ in the firstdifferential amplifier D₁ are connected to the gate of the second outputpull up transistor Q₂₆ in the second differential amplifier D₂. Thesources of the input transistors Q₂₁ and Q₂₂ are connected to the gateof the second pull up transistor Q₁₆ in the first differential amplifierD₁.

Thus, the first differential amplifier D₁ and the second differentialamplifier D₂ each constitute a complementary MOS (CMOS) differentialamplifier having the P channel output pull up transistor and the Nchannel input transistor.

The second output pull up transistors Q₁₆ and Q₂₆ function to acceleratethe charging up of the output ends DA and DA, respectively.

As will be apparent by comparing FIGS. 1 and 4, the conventional senseamplifier shown in FIG. 1 is equivalent to the circuit in which thesecond output pull up transistors Q₁₆ and Q₂₆ and the output amplitudedetermining transistor Q₂₀ are removed from the circuit shown in FIG. 4.

FIG. 5 is a waveform diagram showing an example of the operation of thecircuit shown in FIG. 4. In FIG. 5, the potential of the power supplyV_(CC) is assumed to be about 5 V, and the potential of the ground lineV_(SS) is assumed to be about 0 V. Also, at the beginning, it is assumedthat the bit line BL is at the low potential (L level) of about 2.5 V,and the bit line BL is at the high potential (H level) of about 3 V.Accompanied by the miniaturization of a memory cell as mentioned before,the potential difference between the bit lines becomes as small as 0.5V. By applying the L level to the gate of the first input transistor Q₁₁in the first differential amplifier, the first input transistor Q₁₁ hasa low mutual conductance g_(m) (L), so that the potential at a node ○Cconnected to the gates of the transistors Q₁₃ and Q₁₄ is at a highlevel, causing the P-channel transistors Q₁₃ and Q₁₆ to have a lowmutual conductance g_(m) (L), and causing the N-channel feedbacktransistor Q₁₅ to have a high mutual conductance g_(m) (H). Also,because the H level is applied to the gate of the second inputtransistor Q₁₂, it has a high mutual conductance g_(m) (H).

On the other hand, in the second differential amplifier, the first inputtransistor Q₂₁ has the high mutual conductance g_(m) (H) and,accordingly, the P-channel transistors Q₂₃ and Q₂₄ have the high mutualconductance g_(m) (H). The feedback transistor Q₂₅ has the low mutualconductance g_(m) (L). The second input transistor Q₂₂ has the lowmutual conductance g_(m) (L).

Since the feedback transistor Q₂₅ has the low mutual conductance g_(m)(L), the potential at a node ○B connected to the drain of the transistorQ₂₅ is at a high level. The node ○B is connected to the gate of thesecond output pull up transistor Q₁₆ in the first differential amplifierD₁. Therefore the transistor Q₁₆ has the low mutual conductance g_(m)(L). As a result, in the first differential amplifier D₁, thetransistors Q₁₃ and Q₁₆ have the low mutual conductance g_(m) (L), andthe transistors Q₂₂ and Q₂₅ have the high mutual conductance g_(m) (H),so that the potential at the output end DA is at a low level of about 1V.

Since the feedback transistor Q₁₅ has the high mutual conductance g_(m)(H), the potential at a node ○A connected to the drain of the transistorQ₁₅ is at a low level. The node ○A is connected to the gate of thesecond output pull up transistor Q₂₆ in the second differentialamplifier D₂. Therefore, the transistor Q₂₆ has the high mutualconductance g_(m) (H). As a result, in the second differential amplifierD₂, the transistors Q₂₃ and Q₂₆ have the high mutual conductance g_(m)(H), and the transistors Q₂₂ and Q₂₅ have the low mutual conductanceg_(m) (L), so that the potential at the output end DA is at a high levelof about 3.5 V.

At a time t₁, the pair of bit lines BL and BL are precharged to have thesame potential of 3 V. By this precharging, the transistors Q₁₁, Q₁₃ andQ₁₄ in the first differential amplifier D₁, and the transistor Q₂₂ inthe second differential amplifier D₂ are turned to have the high mutualconductance g_(m) (H). Also, the transistor Q₁₅ is turned to have thelow mutual conductance g_(m) (L).

Then, the potentials of the bit lines BL and BL are inverted inaccordance with the content of the selected memory cell, so that the bitline BL is kept at the high potential of 3 V and the bit line BL isturned to the low potential of 2.5 V. Since the feedback transistor Q₁₅has, at this stage, the low mutual conductance g_(m) (L), the potentialat the node ○A is raised so that the mutual conductance of thetransistor Q₂₆ is lowered. On the other hand, in the second differentialamplifier D₂, the transistors Q₂₁, Q₂₃, and Q₂₄ have, at this stage, thelow mutual conductance g_(m) (L), and the transistors Q₂₂ and Q₂₅ havethe high mutual conductance g_(m) (H). As a result, the potential at thenode ○B is lowered so that the mutual conductance of the transistor Q₁₆for accelerating the charge up of the output end DA is increased. Thepotential at the node ○B is lower than the potential at the node ○Cwhich is also at a low level. Therefore, the second output pull uptransistor Q₁₆ becomes more active than the first output pull uptransistor Q₁₃. As a result, the second output pull up transistor Q₁₆ israpidly turned to be more conductive, accelerating the charge up of theoutuput end DA to the high level of about 3.5 V.

In the second differential amplifier D₂, the transistors Q₂₃ and Q₂₆ areturned to have the low mutual conductance g_(m) (L) and the transistorsQ₂₂ and Q₂₅ are turned to have the high mutual conductance g_(m) (H), sothat the charges stored at the output end DA are discharged through thetransistors Q₂₂ and Q₂₆ to the ground line V_(SS). Thus, the potentialat the output end DA is gradually decreased, and as a result, at a timet₂, the potentials at the output ends DA and DA are inverted.

It will be seen from FIG. 5 that a period Δt between the time t₁ and thetime t₂ is a response period of the sense amplifier SA in response to aninversion of the bit lines. The response period Δt is shortened incomparison with the conventional response period. One reason for this isbecause the rise of the potential at the output end DA is accelerated bythe function of the second output pull up transistor Q₁₆. Another reasonis that the high level of the potential at the output end DA is limitedto a low voltage of about 3.5 V by providing the output amplitudedetermining transistor Q₂₀. The high level of the potential at theoutput end DA is adjustable by adjusting the dimensions of thetransistors Q₁₆ and Q₂₀.

The operation of the sense amplifier SA in response to a potentialchange of the bit line BL from the high level to the low level issimilar to the operation described above.

In the conventional sense amplifier shown in FIG. 1, which does not havethe second output pull up transistors Q₁₆ and Q₂₆ and the outputamplitude determining transistor Q₂₀, the potential at the output end DArises in response to the increase of the mutual conductance of thetransistor Q₀₃ and to the decrease of the mutual conductance of thetransistor Q₀₂. However, as illustrated by a dash curve in FIG. 5, therise of the potential at the output end DA is very slow and the highlevel is higher in comparison with the embodiment of the presentinvention. This is due to the lack of the second output pull uptransistor Q₁₆ and the output amplitude determining transistor Q₂₀.Therefore, a time t₃, at which the potentials of the output ends DA andDA of the dash curves cross, is later than the time t₂ in the embodimentof the present invention.

More precisely, in the conventional sense amplifier shown in FIG. 1,when the bit lines BL and BL are precharged to have the high potentialof about 3 V, the transistors Q₀₁, Q₀₂, Q₀₃, and Q₀₄ have the highmutual conductance g_(m) (H), and the transistor Q₀₅ has the low mutualconductance g_(m) (L). Then when the potential of the bit line BL islowered, the transistor Q₀₂ is turned to have the low mutual conductanceg_(m) (L). As a result, the potential at the output end DA is pulled upthrough the transistor Q₀₃. Therefore, only the second input transistorQ₀₂ changes its state to assist the rise of the potential at the outputend DA. No acceleration to raise the output potential is carried out inthe conventional sense amplifier.

FIG. 6 is a waveform diagram showing another example of the operation ofthe circuit shown in FIG. 4. In FIG. 6, the only difference from FIG. 5is that the pair of bit lines BL and BL are precharged not to the highlevel of about 3 V but to an intermediate level between 3 V and 2.5 V.The operation of the sense amplifier SA in this case is similar to thatdescribed with reference to FIG. 5, and therefore, is not describedhere.

The present invention is not restricted to the above-describedembodiment. Various changes and modifications are possible. For example,in place of the CMOS asymmetrical differential amplifier, any other typeof asymmetrical differential amplifier may be employed within the scopeof the present invention.

From the foregoing description, it will be apparent that, according tothe present invention, by employing two asymmetrical differentialamplifiers having the same circuit configuration, and by connecting themso as to accelerate the charge up of the outputs of the asymmetricaldifferential amplifiers by utilizing nodes whose potentials are changedin response to changes of input potentials, a sense amplifier accordingto the present invention can change its output potential at a higherspeed in comparison with the conventional sense amplifier.

I claim:
 1. A sense amplifier comprisinga pair of differential amplifiercircuits, for receiving complementary input signals and producingcomplementary output signals, each of said differential amplifiercircuits including:a pair of differential input transistors forreceiving said complementary input signals, each said differential inputtransistor having a source connected at a common connecting point of therespective differential amplifier circuit to the source of the otherdifferential input transistor, a gate connected to receive a respectiveone of said complementary input signals, and a drain, wherein saidcomplementary signals applied to a first one of the pair of differentialamplifier circuits have respective phases opposite to the phases of saidcomplementary signals applied to the other of said pair of differentialamplifier circuits; a feedback transistor having a drain connected tosaid commonly connecting point, a source connected to ground, and a gateconnected to said drain of a first one of the differential inputtransistors; first pull up means connected between a power supply and tosaid drain of the second of the differential input transistors; andsecond pull up means including an output pull up transistor having asource and a drain connected between the power supply and the seconddifferential input transistor, wherein each said output pull uptransistor in each said differential amplifier circuit has a gateconnected to receive an output of said feedback transistor in the otherone of said differential amplifier circuits.
 2. A sense amplifier as setforth in claim 1, wherein each of said differential input transistorsand each said feedback transistor is an N channel MOS transistor, andeach said output pull up transistor is a P channel MOS transistor.
 3. Asense amplifier as set forth in claim 2, further comprising an outputamplitude determining transistor connected between the source of bothsaid output pull up transistors and said power supply.
 4. A senseamplifier as set forth in claim 2, further comprising a respective Pchannel MOS transistor in each said differential amplifier circuit, eachhaving its source connected to said power supply, its drain connected tothe drain of the first differential input transistor, and its gateconnected to a control input of the respective first pull up means.
 5. Asense amplifier as set forth in claim 3, wherein said output amplitudedetermining transistor is a P channel MOS transistor having a gateconnected to a ground line.
 6. A sense amplifier as set forth in claim3, wherein said first pull up means comprises a P channel MOS transistorwith its drain connected to the drain of the output pull up transistorof the second pull up means.
 7. A sense amplifier as set forth in claim1, wherein said first pull up means comprises a P channel MOS transistorwith its drain connected to the drain of the output pull up transistorof the second pull up means.